The present invention generally relates to a dynamic random access memory, and in particular to a dynamic random access memory of an address multiplex type. More particularly, the present invention relates to a dynamic random access memory in which a row address signal is released from a latched state in response to an actual change in potential of a word line.
Generally, a dynamic random access memory (hereafter simply referred to as a DRAM) is suitable for obtaining an increased integration density, because it may be constructed of a smaller number of elements than a static random access memory (hereafter simply referred to as a SRAM). Therefore, the cost for manufacturing a DRAM is less than that for manufacturing a SRAM. For the above reasons, DRAMs are widely used as a main memory and various memory devices.
An address multiplex type DRAM has an addressing operation as described below. At the commencement of the addressing operation, a row address strobe signal is switched to a low level (a ground level, for example). Then, an external address signal is latched in response to a rise in level of a latch enable signal. Next the latched external address signal is decoded by a row address decoder to generate a row address, and then one of the word lines of a memory cell array is selected. On the other hand, the external address signal is latched in response to a rise of another latch enable signal, after the row address is latched. At this time, a column address strobe signal is kept at the low level. Then the latched external address signal is decoded to generate a column address, and one of the bit lines is selected. In this manner, a memory cell positioned at an intersection of the designated word line and bit line can be selected. Thereby, a datum can be written into or read out from the designated memory cell. After that, the row address strobe signal is switched to a high level (a positive power source voltage V.sub.DD, for example), and then the selected word line is discharged. During the discharge of the selected word line, the row address is kept latched. Thereafter, the row address is released from the latched state. Finally, the word lines are charged up to the V.sub.DD level for the next read or write operation.
It is noted that the row address must be kept latched during the time when the selected word line is discharged. This is because the selected word line is discharged through the address decoder. If the row address is released from the latched state before the selected word line is completely discharged, an erroneous operation may occur.
Since the row address is supplied to the memory cell array and thereafter the column address is supplied thereto as described above, it is unnecessary to simultaneously enter the row address and the column address into the memory cell array. For this reason, it is possible to use an address line and an address pin commonly for the row and column addresses. This makes it possible to attain a reduced package size and a reduced number of signal lines formed around the DRAM device, so that the density in arrangement of devices on a printed circuit board, can be enhanced.
However, the above conventional DRAM has the following disadvantages. The row address is released from the latched state when a constant time elapses after the rise of the row address strobe signal. This releasing operation is carried out irrespective of the actual change in potential of the selected word line. Therefore, the above constant time must be selected by taking into consideration an operational margin and dispersion of characteristics over DRAM devices due to the production process. That is, the constant time must be selected so as to be equal to or more than a time amounting to the sum of a time when the selected word line is anticipated to become equal to zero potential, and a time margin. For this reason, one cycle of the write or read operation is lengthened by the time margin. This causes a decreased quantity of information to be handled per a unit time.
On the other hand, if the constant time for the release from the row address latch is shortened so as to obtain a reduced time margin, the external address may be released from the latched state before the selected word line completely becomes equal to zero potential. This causes an erroneous operation.